Many engineers are curious about what to learn about Arm architecture.
Table of content below includes fundamentals of Arm architecture that
all of system software engineers should know.
I refer to below link;
[Introducing the Arm architecture]
1 Overview
2 About the Arm architecture
3 What do we mean by architecture?
4 System architecture
5 Architecture and micro-architecture
6 Development of the Arm architecture
* 6.1 Armv8-A
* 6.2 Armv9-A
* 6.3 Annual updates
7 Other Arm architectures
8 Understanding Arm documentation
* 8.1 Where is the documentation?
* 8.2 Which document describes what?
* 8.3 So, what does this mean for me?
* 8.4 What information will I find in each document?
* 8.5 Differences between reference manuals and user guides
9 Common architecture terms
* 9.1 PE Processing Element
* 9.2 IMPLEMENTATION DEFINED
* 9.3 UNPREDICTABLE and CONSTRAINED UNPREDICTABLE
* 9.4 DEPRECATED
* 9.5 RES0/RES1 Reserved, should be Zero/Reserved, should be One
[Armv8-A Instruction Set Architecture]
1 Overview
2 Why you should care about the ISA
3 Instruction sets in the Armv8-A
4 Instruction set resources
5 Simple sequential execution
6 Registers in AArch64
* 6.1 General-purpose registers
* 6.2 Other registers
* 6.3 System registers
7 Data processing
* 7.1 Arithmetic and logic operations
* 7.2 Floating point
** 7.2.1 Is floating point support optional?
* 7.3 Bit manipulation
* 7.4 Extension and saturation
** 7.4.1 Sub-register-sized integer data processing
* 7.5 Format conversion
* 7.6 Vector data
8 Loads and stores
* 8.1 Size
* 8.2 Zero and sign extension
* 8.3 Addressing
* 8.4 Load pair and store pair
* 8.5 Using floating point registers
9 Program flow
* 9.1 Loops and decisions
* 9.1.2 Unconditional branch instructions
* 9.1.3 Conditional branch instructions
* 9.2 Generating condition code
* 9.3 Conditional select instructions
10 Function calls
11 Procedure Call Standard
12 System calls
13 Check your knowledge
14 Related information
* 14.1 Instruction set resources
* 14.2 Procedure Call Standard
* 14.3 Useful links to training
15 Next steps
[Exception model]
1 Overview
2 Privilege and Exception levels
* 2.1. Types of privilege
* 2.2. Memory privilege
* 2.3. Register access
3 Execution and Security states
* 3.1. Execution states
* 3.2. Security state
* 3.3. Realm Management Extension
* 3.4. Changing Execution state
* 3.5. Changing Security state
* 3.6. Implemented Exception levels and Execution states
4 Exception types
* 4.1. Synchronous exceptions
* 4.2. Asynchronous exceptions
* 4.3. IRQ and FIQ
* 4.3.1. Non-maskable interrupts
* 4.4. SError
5 Handling exceptions
* 5.1. Exception terminology
* 5.2. Taking an exception
* 5.3. Routing asynchronous exceptions
* 5.4. Determining which Execution state an exception is taken to
* 5.5. Returning from an exception
* 5.6. Exception stacks
6 The vector tables
7 Check your knowledge
8 Related information
9 Next steps
[Memory Management]
1 Overview
2 What is memory management
* 2.1 Why is memory management needed?
3 Virtual and physical addresses
4 The Memory Management Unit (MMU)
* 4.1 Table entry
* 4.2 Table lookup
* 4.3 Multilevel translation
5 Address spaces
* 5.1 Physical Addresses
* 5.2 Address sizes
* 5.3 Size of virtual addresses
* 5.4 Size of physical addresses
* 5.5 Size of intermediate physical addresses
* 5.6 Address space Identifiers -Tagging translations with the owning process
* 5.7 Virtual Machine Identifiers – Tagging translations with the owning VM
* 5.8 Common not Private
6 Controlling address translation
* 6.1 Translation table format
7 Translation granule
* 7.1 The starting level of address translation
* 7.2 Registers that control address translation
* 7.3 MMU disabled
8 Translation Lookaside Buffer maintenance
* 8.1 Format of a TLB operation
9 Address translation instructions
[Armv8-A memory model]
1 Overview
2 What is a memory model, and why is it needed?
3 Describing memory in Armv8-A
* 3.1. Hierarchical attributes
* 3.2. MMU disabled
4 Memory access ordering
5 Memory types
6 Normal memory
* 6.1. Access ordering
* 6.2. Limits on re-ordering
7 Device memory
8 Describing the memory type
9 Cacheability and shareability attributes
10 Permissions attributes
* 10.1. Privileged accesses to unprivileged data
* 10.2. Execution permissions
11 Access Flag
* 11.1. Updating the AF bit
* 11.2. Dirty state
12 Alignment and endianness
* 12.1. Alignment
* 12.2. Endianness
13 Memory aliasing and mismatched memory types
14 Combining Stage 1 and Stage 2 attributes
14.1.1 Fault handling
[Armv8-A virtualization]
1 Overview
2 Introduction to virtualization
* 2.1 Why is virtualization important?
* 2.2 Standalone and hosted hypervisors
* 2.3 Full virtualization and para-virtualization
* 2.4 Virtual machines and virtual CPUs
3 Virtualization in AArch64
4 Stage 2 translation
* 4.1 What is stage 2 translation?
* 4.2 VMIDs
* 4.3 VMID interaction with ASIDs
* 4.4 Attribute combining and overriding
* 4.5 Emulating Memory-mapped Input/Output (MMIO)
* 4.6 System Memory Management Units (SMMUs)
5 Trapping and emulation of instructions
* 5.1 Presenting virtual values of registers
* 5.2 MIDR and MPIDR
6 Virtualizing exceptions
* 6.1 Enabling virtual interrupts
* 6.2 Generating virtual interrupts
* 6.3 Example of forwarding an interrupt to a vCPU
* 6.4 Interrupt masking and virtual interrupts
7 Virtualizing the Generic Timers
8 Virtualization Host Extensions
* 8.1 Running the Host OS at EL2
* 8.2 Virtual address space
* 8.3 Re-directing register accesses
* 8.4 Exceptions
9 Nested virtualization
* 9.1 Guest Hypervisor access to virtualization controls
10 Secure virtualization
* 10.1 Secure EL2 and the two Intermediate Physical Address spaces
11 Costs of virtualization
[TrustZone for AArch64]
1 Overview
* 1.1 Before you begin
2 What is TrustZone?
* 2.1 TrustZone for Armv8-M
* 2.2 Armv9-A Realm Management Extension
3 TrustZone in the processor
* 3.1 Security States
* 3.2 Switching between Security states
* 3.3 Virtual address spaces
* 3.4 Physical address spaces
* 3.5 Data, instruction and unified caches
* 3.6 Translation Lookaside Buffer
* 3.7 SMC exceptions
* 3.8 Secure virtualization
4 System Architecture
* 4.1 Completers: peripherals, and memories
* 4.2 Enforcing Isolation
* 4.3 Bus requesters
* 4.4 M and R profile Arm processors
* 4.5 Interrupts
* 4.6 Handling interrupts
* 4.7 Debug, trace, and profiling
* 4.8 Other devices
* 4.9 Trusted Base System Architecture
5 Software architecture
* 5.1 Top-level software architecture
* 5.2 Trusting the message?
* 5.3 Scheduling
* 5.4 OP-TEE
* 5.5 Interacting with Non-secure virtualization
* 5.6 Boot and the chain of trust
* 5.7 Boot failures
* 5.8 Trusted Board Boot Requirements
* 5.9 Trusted Firmware
6 Example use cases
* 6.1 Encrypted filesystem
* 6.2 Over the air firmware update
7 Check your knowledge
8 Related information
9 Next steps
[Introducing Arm Confidential Compute Architecture]
1 Overview
* 1.1 Before you begin
2 What is Arm CCA?
* 2.1 Arm CCA requirements
3 Arm CCA extensions
* 3.1 Realms
* 3.2 Realm world and Root world
* 3.3 What is the difference between Arm TrustZone extensions and Arm RME?
4 Arm CCA hardware architecture
* 4.1 Realm world requirements
* 4.2 Memory management for Arm CCA
* 4.3 Attestation
5 Arm CCA software architecture
* 5.1 Software stack overview
* 5.2 Realm Management Monitor
* 5.3 Realm Management Interface
* 5.4 Realm Services Interface
[Arm Confidential Compute Architecture software stack]
1 Overview
* 1.1 Before you begin
* 1.2 Goals
* 1.3 Hardware-software split
2 Software components
* 2.1 Monitor
* 2.2 Realm Management Monitor
3 Realm management
* 3.1 Resource management
* 3.2 Realm creation and attestation
* 3.3 Realm memory management
* 3.4 Realm context switching
* 3.5 Realm interrupts
4 Related information
5 Next steps
[Introduction to security]
1 Introduction to security
2 What do we mean by security?
3 Attacking a system
* 3.1. Types of attack
* 3.2. Different attackers
* 3.3. Threat models and putting it altogether
4 Different solutions for different problems
[Coding for Neon]
1 Overview
2 Load and store: example RGB conversion
3 Load and store: data structures
* 3.1 Syntax
* 3.2 Interleave pattern
* 3.3 Element types
* 3.4 Single or multiple elements
* 3.5 Addressing
* 3.6 Other types of loads and stores
4 Load and store: leftovers
* 4.1 Extend arrays with padding
* 4.2 Overlap data elements
* 4.3 Process leftovers as single elements
* 4.4 Other considerations for leftovers
5 Permutation: rearranging vectors
* 5.1 Permutation guidelines
* 5.2 Alternatives to permutation
6 Permutation: Neon instructions
* 6.1 Move instructions
* 6.2 Reverse instructions
* 6.3 Extraction instructions
* 6.4 Transpose instructions
* 6.5 Interleave instructions
* 6.6 Table lookup instructions
7 Matrix multiplication
* 7.1 The algorithm
* 7.2 Neon registers and data size
* 7.3 Floating-point implementation
* 7.4 Fixed-point implementation
* 7.5 Optimized instruction scheduling
8 Shifting left and right
* 8.1 Shifting vectors
* 8.2 Shifting and inserting
* 8.3 Shifting and accumulation
* 8.4 Instruction modifiers
* 8.5 Available shifting instructions
* 8.6 Example: converting color depth
* 8.6.1 Converting from RGB565 to RGB888
* 8.6.2 Converting from RGB888 to RGB565
8.7 Conclusion
[Introduction to AMBA AXI]
1 Overview
2 What is AMBA, and why use it?
* 2.1 Where is AMBA used?
* 2.2 Why use AMBA?
* 2.3 How has AMBA evolved?
* 2.3.1 AMBA
* 2.3.2 AMBA 2
* 2.3.3 AMBA 3
* 2.3.4 AMBA 4
* 2.3.5 AMBA 5
3 AXI protocol overview
* 3.1 AXI in a multi-manager system
* 3.2 AXI channels
* 3.3 Main AXI features
4 Channel transfers and transactions
* 4.1 Channel handshake
* 4.2 Differences between transfers and transactions
* 4.3 Channel transfer examples
* 4.4 Write transaction: single data item
* 4.5 Write transaction: multiple data items
* 4.6 Read transaction: single data item
* 4.7 Read transaction: multiple data items
* 4.8 Active transactions
5 Channel signals
* 5.1 Write channel signals
* 5.2 Read channel signals
* 5.3 Data size, length, and burst type
* 5.4 Protection level support
* 5.5 Cache support
* 5.6 Response signaling
* 5.7 Write data strobes
* 5.8 Atomic accesses with the lock signal
* 5.9 Quality of service
* 5.10 Region signaling
* 5.11 User signals
* 5.12 AXI channel dependencies
6 Atomic accesses
* 6.1 Locked accesses
* 6.2 Exclusive accesses
* 6.3 Exclusive access hardware monitor operation
* 6.4 Exclusive transaction pairs: both pass
* 6.5 Exclusive transaction pairs: one pass, one fail
7 Transfer behavior and transaction ordering
* 7.1 Examples of simple transactions
* 7.2 Transfer IDs
* 7.3 Write transaction ordering rules
* 7.4 Read transaction ordering rules
* 7.5 Read and write channel ordering
* 7.6 Unaligned transfer start address
* 7.7 Endianness support
* 7.8 Read and write interface attributes
8 Check your knowledge
9 Related information
10 Next steps
[Armv8-A external debug]
1 Overview
* 1.1 Before you begin
2 External debug
* 2.1 External debug interface
3 Debug state
* 3.1 Debug state entry and exit
4 Debug Access Port
5 Enabling external debug
* 5.1 Handshake between the external debugger and the PE
6 External debug events
* 6.1 External debug request event
* 6.2 Halt instruction debug event
* 6.3 Halting step debug event
* 6.4 Exception catch debug event
* 6.5 Reset catch debug event
* 6.6 Software access debug event
* 6.7 OS unlock catch debug event
* 6.8 Breakpoint event
* 6.9 Watchpoint event
7 Embedded Cross Trigger
8 Check your knowledge
9 Related information
[Providing protection for complex software]
1 Overview
* 1.1. Before you begin
2 Stack smashing and execution permissions
3 Return-oriented programming
* 3.1. Pointer authentication
* 3.2. How is the PAC checked?
* 3.3. New instructions
* 3.4. Use of the NOP space
* 3.5. Enabling pointer authentication
4 Jump-oriented programming
* 4.1. What is jump-oriented programming?
* 4.2. Branch target instructions
* 4.3. Enabling branch target checking
* 4.4. How BTI is implemented
* 4.5. X16 and X17
* 4.6. Function entry and return
5 Applying these techniques to real code
* 5.1. Build an image with pointer authentication and branch target identification
* 5.2. Reduction in available gadgets
* 5.3. Effect on code size
6 Detecting memory safety violations
* 6.1. Memory tagging
* 6.2. Tags
* 6.3. Tagged and untagged addresses
* 6.4. What happens when a comparison fails?
* 6.5. Combining memory tagging and pointer authentication
7 Check your knowledge
8 Related information
[AArch64 Programmer's Guides Generic Timer]
1 Overview
* 1.1. Before you begin
2 What is the Generic Timer?
3 The processor timers
* 3.1. Count and frequency
* 3.2. Timer registers
* 3.2.1. Accessing the timers
* 3.3. Configuring a timer
* 3.4. Interrupts
* 3.5. Timer virtualization
* 3.6. Event stream
* 3.7. Summary table
4 System Counter
* 4.1. Counter scaling
* 4.2. Basic Programming
5 External timers
6 Example using Arm Development Studio
7 Check your knowledge
8 Related information
9 Next steps
[Before debugging on Armv8-A]
1 Overview
* 1.1 Before you begin
2 Different types of debug
* 2.1 External debug
* 2.2 Self-hosted debug
* 2.3 Invasive debug
* 2.4 Non-invasive debug
3 Target types
4 Program being debugged
5 Target state
* 5.1 Core or processor is powered down
* 5.2 Core or processor is held in reset
* 5.3 Core or processor is in a different security state
* 5.4 Core or processor is in a different Exception level
6 Initializing a target
* 6.1 Powering up or taking a core or processor out of reset
* 6.2 Unlocking scan chains or devices
* 6.3 Multiplexed signals
* 6.4 Missing connectors
7 Check your knowledge
8 Related information
9 Next steps
[Understanding Trace]
1 Overview
* 1.1. Before you begin
2 What is trace?
* 2.1. Instruction trace
* 2.2. Data trace
* 2.3. Instrumentation trace
* 2.4. System trace
3 What is trace used for?
4 Trace output
* 4.1. On-chip capture
* 4.2. Off-chip capture
5 Trace components
* 5.1. Trace source: Embedded Trace Macrocell
* 5.2. Trace source: Program Trace Macrocell
* 5.3. Trace source: Instrumentation Trace Macrocell
* 5.4. Trace source: System Trace Macrocell
* 5.5. Trace source: Embedded Logic Analyzer
* 5.6. Trace sink: Trace Memory Controller
* 5.7. Trace sink: Trace Port Interface Unit
* 5.8. Trace link: funnel
* 5.9. Trace link: replicator
* 5.10. Trace link: cross trigger network
* 5.11. Timestamp generator
6 Trace infrastructure examples
* 6.1. ETM trace infrastructure examples
* 6.2. Multiple core trace infrastructure example
* 6.3. CTI trace infrastructure example
7 Can trace capture affect a system?
8 Specifications
9 Check your knowledge
10 Related information
[Understanding the Armv8.x and Armv9.x extensions]
1 Overview
2 What do Armv8.x-A and Armv9.x mean?
3 Why do we need the .x extensions?
3.1 Extension naming
4 Processor implementation
5 Armv8.x and Armv9.x extensions and features
* 5.1 Armv8.1-A
* 5.2 Armv8.2-A
* 5.3 Armv8.3-A
* 5.4 Armv8.4-A
* 5.5 Armv8.5-A and Armv9.0-A
* 5.6 Armv8.6-A and Armv9.1-A
* 5.7 Armv8.7-A and Armv9.2-A
* 5.8 Armv8.7-A and Armv9.3-A
6 Which .x extension does my processor implement?
7 Armv8.x-A and the SBSA
8 Check your knowledge
9 Related information
10 Next steps
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