RISC-V (31) 썸네일형 리스트형 [RISC-V]: Interrupt handling - code walkthrough https://elixir.bootlin.com/linux/v6.8-rc1/source/arch/riscv/kernel/entry.S SYM_CODE_START(handle_exception) /* * If coming from userspace, preserve the user thread pointer and load * the kernel thread pointer. If we came from the kernel, the scratch * register will contain 0, and we should continue on the current TP. */ csrrw tp, CSR_SCRATCH, tp bnez tp, .Lsave_context ... /* * MSB of cause diff.. [RISC-V]: Interrupt handling workflow in Linux kernel Interrupt handling routines are architecture-dependent. The way interrupts are managed and processed can vary significantly between different computer architectures. Interrupt handling routines can be different between RISC-V and Armv8. Understanding interrupt handling routines is crucial when dealing with real-time operating systems (RTOS) and the Linux kernel. Since RTOS and Linux kernel rely .. [RISC-V] secret behind 'tp'(X4) register in Linux kernel 'current' macro is mainly used to read 'task_struct' address of current process. arch/riscv/include/asm/current.h register struct task_struct *riscv_current_is_tp __asm__("tp"); static __always_inline struct task_struct *get_current(void) { return riscv_current_is_tp; } #define current get_current() Body of current is 'get_current()' macro. We can deduce that "tp"(X4) holds start address of curr.. RISC-V Instruction Set Specifications [link] From: https://msyksphinz-self.github.io/riscv-isadoc/html/index.html [RISC-V] sudo code for exception handling in Linux kernel ... MP:FFFFFFFF80002FEA| csrrc x9,sstatus,x5 // atomic read and clear bits in CSR. MP:FFFFFFFF80002FEE| csrr x18,sepc MP:FFFFFFFF80002FF2| csrr x19,stval MP:FFFFFFFF80002FF6| csrr x20,scause MP:FFFFFFFF80002FFA| csrr x21,sscratch void handle_exception() { word scause; word offset_vect; void *exception_func; bool interrupt_status; scause = sys_csr_reg_read(scause); // csrr x20,scause interrupt_st.. [RISC-V Kernel build] How to build kernel for visionfive2 kernel ? From: https://doc-en.rvspace.org/VisionFive2/SWTRM/VisionFive2_SW_TRM/swtrm_compiling_linux_kernel%20-%20vf2.html [RISC-V] RISC-V 툴체인으로 리눅스 커널 빌드하기 - 크로스 컴파일(cross-compile) 이번 포스트에서는 RISC-V 툴체인을 설치해 리눅스 커널을 빌드하는 방법을 소개합니다. 먼저 RISC-V 툴체인을 설치하는 명령어를 입력합시다. RISC-V 툴체인 소스를 내려받기 다음 명령어를 입력해 RISC-V 툴체인 소스를 내려받습니다. $ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain 아래는 리눅스 터미널에서 위 명령어를 입력한 후의 출력 결과입니다. 소스를 내려받는데 1시간 정도 걸리네요. austindh.kim:~/src/risc-v_toolchain$ git clone --recursive https://github.com/riscv/riscv-gnu-toolchain Cloning into 'riscv-gnu-too.. 이전 1 2 3 4 다음
